Wafer Level Packaging

Wafer Level Packaging Process

Traditional packing processes involve placing verified good die into lead-frame packages and connecting signal pads to the package via wire bonding. With evolving device technology and chip design the number of I/O pads has increased dramatically creating the need for larger numbers of smaller connection points to the chip. Simultaneously, economic pressures demanded packaging solutions with lower assembly prices. Enter Wafer-Level Packaging, or WLP, sometimes called “bumping” after the visual appearance of the final process.

Based upon the similar techniques as are used for fabricating device interconnect, nearly all wafer-level packaging processes are based upon multi-layer, electroplated metal technology. Unlike the copper damascene processes where the metal is embedded into a permanent dielectric, wafer level packaging makes use of a temporary and patterned template which is typically a photoresist. The process begins by depositing a thin layer of metal to form a barrier and seed layer combination typically referred to as the Under-Bump Metallization, or UBM. Photoresist is then applied over the UBM and openings formed lithographically to create open areas where the metal is to be deposited. When placed into an electroplating bath, metal plates only onto the exposed UBM as it is blocked by the photoresist. The electroplating process consists of more than one process step. While the process flow varies according to the application, a typical process begins with the electro-deposition of a conductive pad or pillar using a low conductivity, inexpensive metal such as copper. This Cu pillar provides the desired amount of compliance needed normal to the wafer surface to ensure effective yields. On top of the pillar, a layer of solder is electro-deposited. Originally containing lead and tin, solders are now predominantly lead free alloys such as SnAg, AuSn, SnAgCu, or others depending upon the needed melting point and application. On occasion, there is an intermetallic reaction between the solder and the pillar, so a barrier layer (often nickel) is deposited in between. After plating, the photoresist is stripped leaving islands of multi-layer metal connected by the UBM. These islands act as a hard mask for the subsequent wet-chemical etch of the exposed UBM. A final thermal treatment allows the solder to reflow into spheroid balls, or bumps. Processing then continues. Later, after test and singulation, die are “flipped” into their receiving packages and a subsequent thermal treatment allows the solder to attach to the package – hence the other names for WLP, C4 (controlled collapse chip connection) or flip-chip. Ultimately, using WLP techniques, much smaller connection features can be created allowing for allowing for very dense I/O to be formed on small die. Further, as a single mask is used to define the bump, the packaging cost is scalable with die size and technology node.

wafer level packaging process using ClassOne Solstice S8

ClassOne Technology designs and builds the Solstice Plating System for several process steps of the wafer-level packaging process that includes, Cu Pillar Plating, Cu Bump Plating, Barrier Plating, and various types of lead-free Solder Plating.


Wafer Level Packaging Process (WLP): Solstice Electroplating System

Cu Pillar Plating, Cu Bump Plating, Barrier Plating: Solstice Electroplating System

Various types of lead-free Solder Plating: Solstice Electroplating System

Solstice LT Plating Tool

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